1. Field of the Invention
The invention relates to a manufacturing method of Schottky barrier diode device made of a compound semiconductor and applied in a high frequency circuit, specifically to a manufacturing method of Schottky barrier diode having a planar configuration to achieve a smaller operation region and a smaller overall chip size.
2. Description of the Related Art
The demand for high frequency devices has been rapidly increasing due to the expanding market for portable telephones and digital satellite communication equipment. Many of such devices include field effect transistors (referred to as FET, hereinafter) employing a gallium arsenide (referred to as GaAs, hereinafter) substrate because of its excellent high frequency characteristics. Typical application in this field includes local oscillation FETs for satellite antenna and monolithic microwave integrated circuits (MMIC) in which a plurality of FETs are integrated for wireless broadband. GaAs Schottky barrier diodes are also used in a base station of cellular phone system.
FIG. 1 is a cross-sectional view including an operation region of a conventional Schottky barrier diode. An n+ epitaxial layer 22 (a silicon impurity concentration of about 5xc3x971018 cmxe2x88x923) having a thickness of about 6 xcexcm is formed on an n+ GaAs substrate 21. An n epitaxial layer 23 (a silicon impurity concentration of about 1.3xc3x971017 cmxe2x88x923) having a thickness of about 350 nm is formed on the n+ epitaxial layer 22. This n epitaxial layer provides as an operation region.
An ohmic electrode 28 makes a ohmic contact with the n+ epitaxial layer 22 and is made of a AuGe (gold-germanium alloy)/Ni (nickel)/Au (gold) metal layer disposed as a first wiring layer. A Ti (titanium)/Pt (platinum)/Au metal 32 serves as a second wiring layer, and is divided into wiring on the anode side and wiring on the cathode side. On the anode side, the Ti/Pt/Au metal layer makes a Schottky contact with the n epitaxial layer 23, and forms a Schottky contact region 31a. The portion of the Ti/Pt/Au metal layer on the anode side above the Schottky contact region 31a is referred to as a Schottky electrode 31. An anode electrode 34 is formed on and completely overlaps with the Schottky electrode 31 and its extension. The anode electrode 34 provides an anode bonding pad 34a and is formed by Au plating using the Schottky electrode 31 and its extension as a plating electrode. A bonding wire 40 is fixed to the anode bonding pad 34a. The Au metal layer serves as a third wiring layer and has a thickness of about 6 xcexcm. The thick Au layer is necessary for providing stress relief during wire bonding. On the cathode side, the cathode electrode 35 provides a cathode bonding pad and is formed of the Au layer. The Ti/Pt/Au metal layer on the cathode side directly contacts the ohmic electrode 28. The edge of the Schottky electrode 31 needs to be on a top surface of a polyimide layer 30 to satisfy photolithographic requirements. Accordingly, a portion of the Schottky electrode 31, near the Schottky region 31a, overlaps by about 16 xcexcm with the polyimide layer 30 formed on the ohmic electrode 28 on the cathode side. The entire substrate and epitaxial layers are at a cathode voltage except the Schottky contact region 31a. The polyimide layer 30 insulates the anode electrode 34 from the substrate 22 and the epitaxial layers. The intersection between the anode electrode 34 and the underlying structure and the intersection between the anode bonding pad 34a and the underlying structure are, in total, about 3900 xcexcm2, which could provide a large parasitic capacitance to the device if the thickness of the polyimide layer 30 is small. Thus, to have a reasonably small parasitic capacitance, the thickness of the polyimide layer must be as large as 6-7 xcexcm even though the polyimide film 30 has a relatively low dielectric constant.
The n epitaxial layer 23 of the lower impurity concentration (1.3xc3x971017 cmxe2x88x923) is necessary for assuring a Schottky contact region 31a with good Schottky characteristics and a high breakdown strength (10V). The ohmic electrode 28 is formed directly on the n+ epitaxial layer 22 for reducing the resistance at the contact. For this reason, a mesa etching process is necessary for exposing the top surface of the n+ epitaxial layer 22. The n+ GaAs substrate 21 underneath the n+ epitaxial layer 22 also has a high impurity concentration, and has a backside electrode made of the AuGe/Ni/Au metal layer for an external contact from the backside.
FIG. 2 is a schematic top view of the conventional Schottky barrier diode having the operation region shown in FIG. 1. The Schottky contact region 31a formed in the n epitaxial layer 23 occupies a central portion of the device. The diameter of this region 31a is about 10 xcexcm. A Schottky contact hole 29 is formed in the center of the Schottky contact region 31a. The Ti/Pt/Au metal layer of the second wiring layer is in direct contact with the n epitaxial layer 23 through the contact hole 29. The ohmic electrode 28 of the first wiring layer surrounds the circular Schottky contact region 31a, and occupies almost a half of the top surface of the device.
The Au metal layer of the third wiring layer provides the bonding pads. On the anode side, the anode bonding pad 34a has a minimum area allowed for one bonding wire 40. On the cathode side, the cathode bonding pad 35a is large enough to provide bonding of multiple wires 40, which is required for reducing the inductance generated at bonding wires. The cathode bonding pad 35a and the cathode electrode 35 are formed directly on the ohmic electrode 8 disposed on the n+ epitaxial layer without the intervening polyimide layer 30. The area of the anode bonding pad 34a is about 40xc3x9760 xcexcm2 and the area for the cathode bonding pad is about 240xc3x9770 xcexcm2.
However, the mesa etching, which is required to expose the n+ epitaxial layer 22 through the n epitaxial layer 23 for the direct contact with the ohmic electrode 28, is not stable enough to provide accurate patterning of the device. For example, the wet etching process used in the mesa etching may remove the oxide film 25 around the contact hole 29, leading to formation of mesa with an irregular shape. Such an irregular mesa structure may cause adverse effects on the Schottky barrier diode, especially the characteristics of the Schottky contact region 31a. 
Furthermore, the polyimide layer 30 has a thickness as large as 6-7 xcexcm to reduce the parasitic capacitance generated between the Schottky electrode 31 and the underlying structures (the epitaxial layers 22, 23 and the substrate 21) at the cathode voltage. To form a step coverage of this thick polyimide layer 30 with the electrodes 31, 34, 35, the edges of the polyimide layer 30 near the Schottky contact region 31a must have a tapered cross-section, as shown in FIG. 1. Such a tapered structure gives rise to a variation of the tapering angle, typically between 30 and 45 degrees. To accommodate this variation, a long separation between the Schottky contact region 31a and the ohmic electrode 28 is required. This separation leads to a large resistance and, thus, poor high frequency characteristics. The device shown in FIG. 1 has a separation of about 7 xcexcm.
It should also be noted that the large area (2400 xcexcm2) of the anode bonding pad 34a further contributes to the increase of the parasitic capacitance of the diode device. Furthermore, the polyimide layer 30 and the thick Au layer are made of expensive materials and their use inevitably increases the production cost.
The invention provides a manufacturing method of Schottky barrier diode including providing a substrate made of a compound semiconductor and epitaxially growing a first layer of a conduction type on the substrate. An insulating region is formed at a predetermined portion of the first layer so that the insulating region reaches the substrate. A metal layer is formed to make a Schottky contact with the first layer and to provide an anode bonding pad.
The invention also provides a manufacturing method of Schottky barrier diode including providing a substrate made of a compound semiconductor and epitaxially growing a first layer of a conduction type on the substrate. An impurity-implanted region of the conduction type is formed at a predetermined portion of the first layer. An insulating region is formed around the impurity-implanted region so that the insulating region reaches the substrate. A metal layer is formed to make a Schottky contact with the first layer and to provide an anode bonding pad.